What is virtual memory in detail — TLB, page tables, huge pages?

Deep dive into virtual memory implementation: Address translation pipeline (x86-64): 64-bit virtual address → 4-level page table walk → physical address. VA bits: [PML4(9)][PDPT(9)][PD(9)][PT(9)][Offset(12)]. Each level indexes 512 entries. Physical address = PTE.frame_number × 4096 + offset. Translation: 4 memory accesses per translation without TLB! TLB (Translation Lookaside Buffer): small, fully associative hardware cache of recent {virtual page → physical frame} mappings. L1 TLB: 64-128 entries, 4-cycle access. L2 TLB: 1024+ entries, ~12-cycle access. TLB hit: 1 cycle extra. TLB miss: 4 memory accesses (full page table walk). TLB hit rate: 99%+ for most workloads. TLB shootdown: when OS modifies a page table entry, it must invalidate the TLB entry on ALL CPUs. Uses Inter-Processor Interrupts (IPIs) — expensive in multiprocessor systems. PCID (Process Context Identifier): tag each TLB entry with the process ID — no need to flush entire TLB on context switch. Significant performance improvement. Intel introduced in Westmere; Linux uses since 4.14. Huge pages (large pages): instead of 4KB pages, use 2MB or 1GB pages. Fewer TLB entries needed to cover the same memory. Huge page pros: fewer TLB misses, fewer page table levels, less page table memory. Cons: internal fragmentation (wasted space in huge page), harder to allocate physically contiguous memory. Linux huge pages: explicit: mmap(, 2MB, MAP_HUGETLB). Transparent Huge Pages (THP): kernel automatically converts small pages to huge pages when beneficial. Critical for databases (PostgreSQL, MySQL, MongoDB benefit greatly).