Digital Logic Design MCQ
Test your Digital Logic Design knowledge with 100 multiple choice questions covering fundamentals to advanced concepts, with instant feedback and explanations.
What is a "logic gate"?
2What is the output of an "AND" gate when both inputs are 1?
3What is the output of an "OR" gate when both inputs are 0?
4What does a "NOT" gate (inverter) do?
5What is the difference between a "NAND" gate and an "AND" gate?
6What is a "truth table"?
7What is the binary representation of the decimal number 5?
8What is "Boolean algebra"?
9What is a "half adder" used for?
10What is the difference between a "half adder" and a "full adder"?
11What is a "multiplexer" (MUX)?
12What is a "demultiplexer" (DEMUX)?
13What is the difference between "combinational" and "sequential" logic circuits?
14What is a "flip-flop" in digital logic?
15What is the purpose of a "clock signal" in sequential digital circuits?
16What is a "register" in digital logic?
17What is the "hexadecimal" number system, and why is it commonly used in digital design?
18What is "two's complement" representation used for?
19What is a "decoder" circuit?
20What is an "encoder" circuit, and how does it relate to a decoder?
21What is the function of a "comparator" circuit in digital logic?
22What is the "De Morgan's theorem" used for in digital logic?
23What is a "7-segment display" commonly used for?
24What is "BCD" (Binary-Coded Decimal)?
25What does "XOR" (exclusive OR) gate output when its two inputs are different?
26What is the purpose of a "tri-state buffer" in digital circuits?
27What is the difference between "synchronous" and "asynchronous" sequential circuits?
28What is a "counter" circuit used for in digital logic?
29What is a "shift register"?
30What is the function of an "SR latch" (Set-Reset latch)?
31What is "fan-out" in digital logic design?
32What is the purpose of "propagation delay" in a logic gate?
33What is a "universal gate," and give an example?
34What is the role of a "Karnaugh map" (K-map)?
35What is the difference between "active high" and "active low" signals?
36What is the purpose of a "pull-up resistor" in a digital logic circuit?
37What is a "programmable logic device" (PLD), such as a PAL or PLA?
38What does "FPGA" stand for, and what is it used for?
39What is the purpose of "ASIC" (Application-Specific Integrated Circuit)?
40What is the maximum decimal value that can be represented by a 4-bit unsigned binary number?
What is the difference between an "SR flip-flop" and a "D flip-flop"?
2What is a "JK flip-flop," and how does it resolve the issue present in SR flip-flops?
3What is the difference between a "ripple carry adder" and a "carry-lookahead adder"?
4What is "setup time" and "hold time" with respect to flip-flops?
5What is "metastability" in digital circuits, and when is it most likely to occur?
6What is the purpose of "synchronizers" when interfacing two circuits operating on different, unrelated clocks?
7What is the difference between a "Moore" and a "Mealy" finite state machine (FSM)?
8What is a "Gray code," and why is it useful in digital systems?
9What is the purpose of "clock skew" management in synchronous digital circuit design?
10What is the function of a "PLA" (Programmable Logic Array) compared to a "PAL" (Programmable Array Logic)?
11What is "hazard" in a combinational logic circuit, and what is one type?
12What is the purpose of "address decoding" in a memory system?
13What is the difference between "static RAM" (SRAM) and "dynamic RAM" (DRAM) at the circuit level?
14What is the purpose of "state minimization" when designing a finite state machine?
15What is a "Schmitt trigger," and why is it used in digital input circuits?
16What is the purpose of an "edge-triggered" versus "level-triggered" (level-sensitive) flip-flop or latch?
17What is "glue logic," and why might it be needed in a digital system design?
18In a "Verilog" or "VHDL" hardware description language, what is the key difference between "blocking" and "non-blocking" assignments (in Verilog) when modeling sequential logic?
19What is the purpose of a "watchdog timer" implemented in digital hardware?
20What is the difference between a "Mealy machine" output glitch risk and a "Moore machine" in terms of asynchronous inputs?
21What does "don't care" condition mean in a truth table or Karnaugh map, and how is it used?
22What is "clock gating," and why is it used in low-power digital design?
23What is the purpose of a "parity bit" in digital data transmission?
24What is the difference between a "ring counter" and a "Johnson counter"?
25What is the purpose of "scan chains" (e.g., scan-based DFT) in digital IC testing?
26What is the difference between "1's complement" and "2's complement" representations of negative numbers?
27What is the role of a "decoder" in implementing a "read-only memory" (ROM) using combinational logic?
28What is the significance of "timing diagrams" in digital circuit analysis?
29What is "wired-OR" (or open-collector/open-drain) logic, and what is one common use?
30What is "logic synthesis" in the context of digital design using hardware description languages (HDLs)?
31What is "Excess-3" code, and how is it related to BCD?
32What is a "race condition" in an asynchronous sequential circuit?
33How can a multiplexer be used to implement an arbitrary Boolean function of its select lines?
34What is the difference between a "SIPO" and a "PISO" shift register?
35What is the purpose of "Booth's algorithm" in digital arithmetic circuits?
36What is the difference between "memory access time" and "memory cycle time"?
37When multiple devices share a common tri-state bus, what mechanism is used to ensure only one device drives the bus at a time, and what happens if this is violated?
38In sequential circuit design, what is the purpose of a "state table" (also called a state transition table)?
39What is the difference between a "synchronous counter" and an "asynchronous (ripple) counter"?
40What is a "BCD adder," and why can't a standard binary adder be used directly to add two BCD digits?
In FPGA design, what is the purpose of a "look-up table" (LUT) within a configurable logic block?
2What is the significance of "static timing analysis" (STA) in digital IC design, and what two main constraints does it check?
3What is "clock domain crossing" (CDC), and what are common issues that must be addressed?
4What is the difference between "latch-based" and "flip-flop-based" (master-slave) sequential designs, and what timing issue is unique to latches?
5What is "dynamic power" versus "static (leakage) power" dissipation in CMOS digital circuits?
6In sequential circuit design, what is a "one-hot encoding" of states, and what trade-off does it represent compared to "binary encoding"?
7What is "retiming" as a sequential circuit optimization technique?
8What is the purpose of "formal verification" (e.g., model checking or equivalence checking) in digital design, as opposed to simulation-based verification?
9What is the concept of "false paths" in static timing analysis, and why must they be explicitly identified?
10In asynchronous FIFO design for clock domain crossing, why are "Gray-coded" pointers commonly used for the read and write pointers?
11What is "voltage scaling" (e.g., dynamic voltage and frequency scaling, DVFS) used for in digital chip design, and what relationship does it exploit?
12What is the role of "scan-based" Automatic Test Pattern Generation (ATPG) in detecting manufacturing defects, and what fault model is commonly targeted?
13What is the difference between "synchronous reset" and "asynchronous reset" for flip-flops, and what is a key trade-off?
14What is "physical synthesis," and how does it differ from traditional logic synthesis?
15What is "power-on reset" (POR) circuitry, and why is it important in digital systems?
16What is "logical equivalence checking" (LEC) used for when comparing an RTL description to a synthesized gate-level netlist?
17In the context of "multi-cycle paths" in static timing analysis, what does it mean for a path to be specified as multi-cycle, and why might a designer do this?
18What is "soft error" susceptibility in digital circuits, and what mitigation techniques are commonly used in high-reliability designs?
19What is the significance of "IR drop" (voltage drop) analysis in chip power distribution network design?
20What is "functional coverage" in the context of verification, and how does it differ from "code coverage"?