Digital Logic Design MCQ

Explanation

Logic gates (AND, OR, NOT, etc.) are the fundamental components of digital circuits, implementing Boolean functions on binary (0/1) inputs.

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An AND gate outputs 1 only when ALL of its inputs are 1; otherwise it outputs 0.

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An OR gate outputs 1 if at least one input is 1; if all inputs are 0, the output is 0.

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The NOT gate (inverter) is a single-input gate that produces the logical complement of its input.

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NAND (NOT-AND) outputs 0 only when all inputs are 1 (the opposite of AND), and 1 otherwise — it is the logical complement of an AND gate's output.

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Truth tables exhaustively list every combination of input values along with the resulting output, fully defining the behavior of a logic function or gate.

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5 in binary is 101, since 1×4 + 0×2 + 1×1 = 5.

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Boolean algebra, developed by George Boole, provides the mathematical foundation for digital logic, using operations like AND, OR, and NOT on binary variables.

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A half adder takes two single-bit inputs and produces a sum bit and a carry bit, but cannot account for a carry-in from a previous addition (unlike a full adder).

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Full adders can be chained together (ripple carry) to add multi-bit numbers because each stage accepts a carry-in from the previous stage, which half adders cannot do.

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A multiplexer (MUX) acts like a switch, routing one of many inputs to a single output line, with the selection controlled by additional "select" input lines.

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A demultiplexer is the opposite of a multiplexer — it takes one input and directs it to a chosen output line among several, determined by select lines.

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Combinational logic (like adders, multiplexers) is "memoryless" — output depends only on current inputs — while sequential logic (like flip-flops, counters) incorporates feedback and memory, so output depends on history as well.

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Flip-flops (like SR, D, JK, T types) are the building blocks of sequential circuits, each capable of storing a single bit and changing state on clock edges or input changes.

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The clock signal provides a common timing reference so flip-flops and registers update their states in a coordinated, predictable manner, avoiding race conditions between components.

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Registers are collections of flip-flops, each storing one bit, that together can hold a multi-bit value (e.g., an 8-bit or 32-bit register), commonly used in CPUs.

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Hexadecimal is convenient in digital systems because each hex digit corresponds exactly to a 4-bit binary group (nibble), making it much more compact and readable than long binary strings.

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Two's complement allows negative numbers to be represented such that standard binary addition circuits can correctly handle both addition and subtraction of signed integers without special-casing.

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Decoders take an n-bit binary input and activate one of up to 2^n output lines, commonly used for memory address decoding or driving displays.

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Encoders compress information from many input lines into a compact binary code (e.g., an 8-to-3 encoder converts one of 8 active inputs into a 3-bit code), the reverse operation of a decoder.

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Digital comparators take two binary inputs and produce outputs indicating their relative magnitude (greater than, less than, or equal), useful in arithmetic and control logic.

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De Morgan's theorems state that NOT(A AND B) = (NOT A) OR (NOT B), and NOT(A OR B) = (NOT A) AND (NOT B) — useful for simplifying expressions and converting between gate types.

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7-segment displays use seven segments (and sometimes a decimal point) that can be individually lit to form numerals 0-9 and some letters, commonly driven by a BCD-to-7-segment decoder circuit.

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In BCD, each decimal digit 0-9 is represented by its 4-bit binary equivalent (0000-1001), making conversion to/from decimal straightforward, though it is less space-efficient than pure binary.

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An XOR gate outputs 1 when its inputs differ (one is 0 and the other is 1), and outputs 0 when both inputs are the same.

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The high-impedance state effectively disconnects the buffer's output from the bus, allowing multiple tri-state buffers to share a common bus line without electrical conflicts, as long as only one drives the line at a time.

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Synchronous circuits use a clock to coordinate state changes at predictable intervals, simplifying design and timing analysis, while asynchronous circuits react immediately to input changes, which can be faster but harder to design correctly.

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Counters (built from flip-flops) increment or decrement their stored value with each clock pulse, used in applications like frequency division, timers, and sequencing control signals.

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Shift registers move data through a chain of flip-flops on each clock pulse, useful for serial-to-parallel conversion, data storage, and implementing certain arithmetic operations.

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The SR latch is one of the simplest sequential storage elements; setting "S" sets the output to 1, setting "R" resets it to 0, and with neither active, it retains ("latches") its previous value.

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Fan-out specifies how many other gate inputs a given output can drive while maintaining correct voltage levels; exceeding this limit can cause signal degradation and unreliable operation.

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Every logic gate has a small but non-zero propagation delay between an input change and the resulting output change, which accumulates through circuits and affects the maximum clock speed of sequential designs.

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NAND and NOR gates are called "universal" because any Boolean function (AND, OR, NOT, XOR, etc.) can be constructed using only NAND gates (or only NOR gates), which is useful for manufacturing simplicity.

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K-maps provide a visual method for simplifying Boolean expressions by identifying groups of adjacent 1s (or 0s) in a truth table, leading to a minimized expression that requires fewer logic gates.

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The naming convention "active high" or "active low" indicates which logic level (1 or 0) represents the "asserted" or "triggering" state of a signal — often denoted with a bar or "n" suffix for active-low signals.

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Without a pull-up resistor, an unconnected digital input could float to an unpredictable voltage, potentially being read as either 0 or 1; the pull-up resistor biases it to a known logic-high state by default.

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PLDs (like PALs, PLAs, and later FPGAs) allow designers to implement custom digital logic functions by configuring the device, offering flexibility compared to fixed-function chips.

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FPGAs consist of an array of configurable logic blocks and interconnects that can be programmed (often using hardware description languages like VHDL or Verilog) to implement custom digital circuits.

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ASICs are designed and fabricated for a specific purpose (e.g., a cryptocurrency mining chip), offering high performance and efficiency for that task but lacking the flexibility of general-purpose or reprogrammable chips like FPGAs.

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A 4-bit unsigned number can represent 2^4 = 16 distinct values, ranging from 0 to 15 (binary 1111 = decimal 15).

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The D flip-flop is often built from an SR (or JK) flip-flop with added logic to ensure S and R are never both 1 simultaneously, simplifying design by guaranteeing a well-defined next state based purely on the D input.

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The "toggle" behavior when J=K=1 makes the JK flip-flop more versatile than the SR flip-flop, as it avoids the undefined state and enables straightforward implementation of toggle (T) flip-flops and counters.

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In a ripple carry adder, each stage must wait for the carry from the previous stage, causing delay to grow linearly with the number of bits; carry-lookahead logic precomputes carries based on input patterns, significantly reducing this delay for wider adders.

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Violating setup or hold time requirements can cause a flip-flop to enter a metastable or incorrect state, so digital designs must ensure data signals are stable for the required windows around each clock edge.

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Metastability is a major concern in asynchronous (multi-clock-domain) designs, often mitigated using synchronizer circuits (e.g., chains of flip-flops) to allow the unstable state to resolve before being used.

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When a signal crosses from one clock domain to another, there's a risk of sampling it during a transition (metastability); a synchronizer chain gives the signal extra clock cycles to settle to a stable value before being used by the receiving logic.

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Because Mealy machine outputs can react immediately to input changes (within the same clock cycle), they can sometimes produce outputs faster than Moore machines, but Moore machines are often considered simpler to design and analyze since outputs are stable for a full clock cycle.

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In standard binary, transitioning between certain values (e.g., 0111 to 1000) changes multiple bits at once; if these transitions aren't perfectly synchronized (as in mechanical encoders), incorrect intermediate values can be read. Gray code avoids this by changing only one bit between consecutive values.

Explanation

Because the clock signal must physically travel through wires to reach each flip-flop, slight differences in arrival time (skew) can occur due to varying wire lengths or loading; excessive skew can violate timing constraints between cooperating flip-flops, so clock distribution networks are carefully designed to minimize it.

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The trade-off between PLAs and PALs reflects flexibility versus simplicity/speed: PLAs allow more complex function implementations due to their dual programmable arrays, while PALs are simpler (and historically cheaper/faster) due to a fixed OR stage.

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Because different signal paths through a circuit can have different delays, an output that should logically remain stable during a transition might momentarily glitch (a hazard); these can be eliminated by adding redundant logic terms identified via K-maps.

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In systems with multiple memory chips or banks, address decoders use higher-order address bits to determine which chip/bank is being addressed, while lower-order bits select the specific location within that chip.

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SRAM is faster and doesn't need refreshing (used for cache) but uses more transistors per bit, making it more expensive/larger; DRAM is denser and cheaper per bit (used for main memory) but requires periodic refresh circuitry to maintain stored charge.

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By identifying states that are functionally equivalent (indistinguishable from external behavior), a designer can reduce the state count, potentially reducing the number of flip-flops (state bits) and simplifying the resulting combinational logic.

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The hysteresis in a Schmitt trigger (different thresholds for rising vs. falling transitions) prevents rapid, multiple switching ("chattering") caused by noise near a single threshold, producing clean digital output from noisy or slow analog inputs.

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Edge-triggering provides more precise, single-event state changes synchronized to a specific clock transition, which is generally preferred in modern synchronous designs to avoid issues like "race-through" that can occur with level-sensitive latches.

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Glue logic bridges incompatibilities between major components (e.g., converting an active-low signal to active-high, or adapting bus widths), often implemented with simple gates or small programmable devices.

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Using non-blocking assignments (<=) for sequential (clocked) logic in Verilog ensures all flip-flops appear to update simultaneously based on their values before the clock edge, correctly modeling real hardware behavior, while blocking assignments (=) are typically used for combinational logic.

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If the main logic fails to "feed" (reset) the watchdog timer within its timeout period — perhaps due to a fault — the watchdog triggers a system reset, helping recover from unexpected lockups.

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Because Mealy outputs are combinational functions of both state and input, rapidly changing inputs can cause the output to momentarily reflect intermediate, unintended combinations before settling — a consideration when output glitches matter (e.g., driving other asynchronous logic).

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Don't care terms give the designer freedom when grouping terms in a K-map; choosing the value (0 or 1) that allows the largest possible groupings leads to a more simplified (fewer-gate) implementation.

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Since switching the clock input of unused flip-flops/registers consumes dynamic power even if their data doesn't change, gating off the clock to idle blocks reduces unnecessary power usage — a common technique in modern low-power chip design.

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Parity checking is a simple error-detection scheme: if the received data's parity doesn't match the expected value, a single-bit error is detected (though it cannot identify which bit, and can't detect even numbers of bit errors).

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The "twist" (feeding back the inverted output) in a Johnson counter doubles the number of unique states compared to a standard ring counter with the same number of flip-flops, at the cost of slightly more complex output decoding.

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Design-for-Test (DFT) techniques like scan chains improve manufacturing test coverage by giving external test equipment controllability and observability of internal flip-flop states, which would otherwise be difficult to access directly.

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2's complement is preferred in most modern systems because it has a single representation for zero and allows addition/subtraction circuits to work uniformly for both positive and negative numbers without special handling.

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A basic ROM can be thought of as a decoder (selecting one row based on the address) connected to a fixed pattern of connections representing the stored data, so that activating a row outputs the corresponding stored bit pattern.

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Timing diagrams visualize the relationships between clock edges, input changes, and output responses over time, helping identify issues like setup/hold violations, race conditions, or incorrect sequencing in a design.

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Open-collector/open-drain outputs allow multiple devices to share a single bus line safely — any device can pull the line low, and a pull-up resistor returns it high when no device is actively driving it low — commonly used in protocols like I2C for shared signal/interrupt lines.

Explanation

Synthesis tools take HDL code (e.g., Verilog/VHDL) describing desired functionality and automatically generate an equivalent network of logic gates and flip-flops, optimized for criteria like area, speed, or power, targeting a specific technology (FPGA/ASIC).

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Excess-3 is formed by adding 3 (0011) to each BCD digit; being self-complementing (the code for 9's complement of a digit is the bitwise complement of its Excess-3 code) makes it useful for decimal subtraction circuits.

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In asynchronous circuits, if multiple state variables must change at once, differing propagation delays can cause the circuit to settle into different final states depending on which signal changes first — a "critical race" that designers must avoid through careful state assignment.

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Since a multiplexer routes one of its data inputs to the output based on the select lines, setting each data input to the desired truth-table output value for that select combination directly realizes the function — a technique sometimes used for quick combinational logic implementation.

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SIPO registers are often used to convert a serial data stream into parallel form (e.g., for driving multiple LEDs from one data line), while PISO registers convert parallel data into a serial stream (e.g., for transmitting data over a single wire).

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By examining pairs of bits and recoding sequences of consecutive 1s as a single subtraction followed by an addition, Booth's algorithm can reduce the number of partial products needed compared to naive shift-and-add multiplication, especially for operands with long runs of 1s.

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For technologies like DRAM, after an access the memory array may need additional time (e.g., to precharge bit lines) before another access can begin, so the cycle time (which determines maximum operation rate) can exceed the raw access time.

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Enable signals (often from a bus arbiter or address decoder) ensure only one tri-state driver is active at a time; if two drivers with opposing logic levels are active simultaneously, the resulting contention can produce invalid voltage levels and increased power dissipation/heat.

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The state table systematically captures all present-state/input combinations and their corresponding next-state/output values, from which the designer can derive the Boolean equations needed for the next-state and output logic of the FSM.

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Ripple counters are simpler (fewer gates) but suffer from cumulative propagation delay as the carry ripples through each stage, and can produce transient incorrect output values during transitions; synchronous counters avoid this by clocking all flip-flops together, at the cost of additional logic to compute each flip-flop's next state.

Explanation

Because BCD only uses codes 0000-1001 (0-9) for each digit, a binary sum of two digits that falls between 1010 (10) and 10011 (19) is not a valid BCD representation; adding 6 corrects the result back into valid BCD range with the proper carry into the next digit position.

Explanation

Modern FPGAs implement combinational logic primarily using small LUTs (e.g., 6-input LUTs), which can be configured to represent any function of their inputs by storing the corresponding truth table values, providing the flexibility to implement diverse logic.

Explanation

STA analyzes all possible paths in a design (without needing input vectors) to ensure that data arrives at flip-flops within the required setup and hold windows relative to the clock, which is essential for closing timing on large designs where exhaustive simulation is infeasible.

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When signals move between clock domains with no fixed phase relationship, naive direct connections risk metastability and data corruption; designers use techniques like multi-flop synchronizers (for single bits), asynchronous FIFOs (for buses/data streams), or gray-coded pointers to safely transfer data across domains.

Explanation

Because a transparent latch passes its input to its output whenever enabled, connecting latches directly in series can allow data to "race through" multiple stages within one clock pulse if the pulse is too wide; master-slave flip-flop construction (using two latches with complementary clock phases) avoids this by ensuring data changes only on a clock edge.

Explanation

In advanced (smaller) process technologies, leakage (static) power has become a significant fraction of total chip power even when circuits are idle, leading to techniques like power gating and multi-threshold transistors to reduce leakage, in addition to traditional dynamic power reduction techniques like clock gating and voltage scaling.

Explanation

One-hot encoding trades flip-flop count (one per state, versus log2(N) for binary encoding of N states) for simpler combinational logic, since each state corresponds to exactly one flip-flop being set — often advantageous in FPGAs where flip-flops are plentiful but LUT logic is the bottleneck.

Explanation

By moving registers across combinational logic boundaries (while preserving the number of registers along any cyclic path and overall I/O behavior), retiming can balance the delay between pipeline stages, often improving achievable clock frequency without altering the circuit's logical function.

Explanation

While simulation can only check the specific scenarios tested, formal techniques like equivalence checking (proving two representations of a design are functionally identical) or model checking (proving a property holds for all reachable states) can provide exhaustive correctness guarantees for the properties checked, though they can face scalability challenges on very large designs.

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Without identifying false paths (using "set_false_path" or similar constraints), STA might flag violations on paths that can never actually propagate a critical transition due to the design's functional behavior, potentially leading designers to waste effort over-optimizing paths that don't matter in practice.

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When a pointer value is sampled by logic in a different clock domain, a standard binary counter could have multiple bits changing simultaneously, risking the receiver sampling an invalid intermediate value; Gray code's single-bit-change property ensures any sampled value is either the old or new value, never an invalid combination, when combined with per-bit synchronizers.

Explanation

Because dynamic power is approximately proportional to V^2 × f, reducing both voltage and frequency during low-demand periods can yield substantial power savings (since power drops roughly with the cube of the scaling factor if both are reduced together), which is why DVFS is widely used in mobile and embedded processors.

Explanation

The stuck-at fault model is a simplified abstraction of physical defects (like shorts or opens) that is computationally tractable for automated tools; ATPG generates patterns that, combined with scan chains for controllability/observability, can detect a high percentage of such faults, providing a manufacturing test quality metric (fault coverage).

Explanation

Asynchronous resets can immediately force a known state (useful at power-up) but the "reset release" itself can cause metastability if not synchronized to the clock; synchronous resets avoid this but require a running clock and add the reset signal to the synthesis timing paths as part of the data logic.

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As technology nodes shrink, interconnect (wire) delays often dominate over gate delays, making it important to consider physical placement during optimization; physical synthesis tools iterate between logical optimization and physical placement/routing estimates to achieve better timing closure than purely logical optimization followed by separate place-and-route.

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Without a reliable POR, flip-flops and other state elements might power up in random or unpredictable states, potentially leading to erratic behavior; POR circuits typically monitor the supply voltage and hold the system in reset until voltage is stable and sufficient for reliable operation.

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After synthesis, placement, and various optimizations, LEC mathematically verifies that the resulting gate-level netlist computes the same functions as the original RTL (for all inputs), catching potential synthesis tool bugs or unintended behavioral changes without needing to simulate every possible scenario.

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By default, STA assumes data must propagate and be captured within a single clock cycle; if the design logic ensures a path's result is only used/sampled every N cycles (e.g., due to an enable signal), specifying it as an N-cycle multi-cycle path relaxes the timing requirement, which can help close timing on otherwise-critical paths without functional impact.

Explanation

As transistor sizes shrink, circuits become more susceptible to transient upsets from particle strikes; in safety-critical or space applications, techniques like ECC memory, redundant computation with majority voting (TMR), and specially designed radiation-tolerant cells help maintain reliability despite soft errors.

Explanation

As current flows through the resistive metal traces of the power grid, voltage drops occur (V=IR); if certain regions experience excessive drop, the effective supply voltage to cells in that region decreases, which can slow down switching speed (affecting timing) or, in extreme cases, cause functional failures — so power grid design includes IR drop analysis and mitigation (e.g., wider power straps).

Explanation

100% code coverage doesn't guarantee all important functional scenarios (e.g., specific combinations of states and inputs, corner cases) have been tested; functional coverage is explicitly defined by verification engineers to track whether these scenarios — often the ones most likely to reveal design bugs — have been exercised.