What is "dynamic power" versus "static (leakage) power" dissipation in CMOS digital circuits?
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The correct answer is A) Dynamic power is consumed when transistors switch (charging/discharging capacitances), proportional to activity, voltage squared, and frequency; static power is leakage consumed continuously even when idle, more significant at smaller nodes
Correct Answer
Dynamic power is consumed when transistors switch (charging/discharging capacitances), proportional to activity, voltage squared, and frequency; static power is leakage consumed continuously even when idle, more significant at smaller nodes
In advanced (smaller) process technologies, leakage (static) power has become a significant fraction of total chip power even when circuits are idle, leading to techniques like power gating and multi-threshold transistors to reduce leakage, in addition to traditional dynamic power reduction techniques like clock gating and voltage scaling.