Computer Architecture & Organization MCQ

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The CPU is the "brain" of the computer, fetching, decoding, and executing instructions, while memory and storage handle data, and peripherals handle I/O.

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The ALU is a digital circuit within the CPU that performs arithmetic (add, subtract) and bitwise logical operations, forming the computational core of instruction execution.

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RAM (Random Access Memory) holds data and instructions actively used by running programs and is cleared on power loss, while ROM (Read-Only Memory) retains its contents permanently, commonly storing firmware like the BIOS.

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Registers are the fastest storage available to a CPU, holding operands, addresses, and intermediate results during instruction execution — much faster than accessing RAM.

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The instruction cycle is the fundamental operation of a CPU: fetch the next instruction from memory, decode it to determine the required operation, then execute it — repeating continuously.

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Cache memory exploits the principle of locality — programs tend to access the same or nearby data repeatedly — by keeping recently used data closer to the CPU, which is much faster than accessing main RAM.

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Primary storage (RAM) is fast but loses data on power-off and is used for active programs; secondary storage (HDD/SSD) is slower but retains data persistently, used for files and installed programs.

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Buses (data bus, address bus, control bus) are the "highways" that allow the CPU, memory, and peripherals to exchange information within a computer system.

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Clock speed determines how many cycles per second the CPU can perform; a higher clock speed generally means more instructions can be processed per second, though actual performance also depends on architecture.

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The ISA is the interface between hardware and software — it specifies what operations a CPU can perform, allowing compilers and assembly programmers to target a specific processor family (e.g., x86, ARM).

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CISC processors (like x86) aim to do more per instruction with complex hardware, while RISC processors (like ARM) use simpler instructions that are easier to pipeline and optimize, often resulting in higher efficiency per cycle.

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The bit (binary digit) is the fundamental unit of digital information; bytes (8 bits) are the standard unit for representing characters and addressing memory in most computer architectures.

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Binary maps naturally onto the two-state nature of electronic switches (transistors), making it the foundation for representing all data and instructions in digital computers.

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The control unit orchestrates the fetch-decode-execute cycle, telling other components (ALU, registers, memory) what to do and when, based on the instruction being processed.

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The motherboard houses the CPU socket, memory slots, expansion slots, and connectors, providing the physical and electrical pathways (buses) that link all major components together.

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I/O devices allow data to enter (input, e.g., keyboard) and leave (output, e.g., display) the computer system, and are managed by I/O controllers and device drivers.

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After each instruction is fetched, the program counter is updated (usually incremented) to point to the next instruction, ensuring sequential execution unless altered by a jump or branch instruction.

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A 64-bit architecture can process data in 64-bit chunks and address a much larger memory space than a 32-bit architecture, which is limited to about 4 GB of addressable memory.

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Firmware (such as BIOS/UEFI) is stored in non-volatile memory and runs before the operating system loads, performing hardware initialization and providing low-level control routines.

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Ports (USB, HDMI, Ethernet, etc.) provide standardized physical and electrical interfaces for connecting peripherals and transferring data or signals between the computer and external devices.

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The address width determines the maximum number of unique memory locations a system can reference; 2^32 addresses (about 4 billion) limits 32-bit systems to roughly 4 GB, while 64-bit systems support a vastly larger range.

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Peripherals extend a computer's functionality by providing input, output, or storage capabilities beyond the core processing components (CPU, memory, motherboard).

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Virtual memory uses a portion of secondary storage (like a "page file" or "swap") as an extension of RAM, allowing the system to run more or larger programs than physical RAM alone would permit, managed via paging.

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Overclocking pushes a CPU beyond its default frequency for more performance, but it generates more heat and can reduce stability or lifespan if not managed with adequate cooling.

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Multi-core processors allow true parallel execution of multiple tasks or threads, improving performance for multitasking and multi-threaded applications compared to a single-core design.

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CPUs generate significant heat during operation; heat sinks (often paired with fans) increase the surface area for heat dissipation, helping maintain safe operating temperatures.

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SSDs use NAND flash memory for storage, providing faster access times and better durability (no moving parts) compared to HDDs, which rely on mechanical spinning disks and read/write heads.

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GPUs contain many simple cores optimized for parallel processing, making them ideal for graphics rendering and, increasingly, for tasks like machine learning and scientific computing that benefit from parallelism.

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Machine code consists of binary instructions specific to a CPU's instruction set, directly executable by the hardware — higher-level languages must be compiled or interpreted down to machine code to run.

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Assembly language uses human-readable mnemonics (e.g., MOV, ADD) that map closely to machine instructions; an assembler converts this into the binary machine code the CPU executes.

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The address bus specifies "where" in memory to read/write, while the data bus carries "what" data is being transferred — together they enable the CPU to access specific memory locations.

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Throughput measures how much work (e.g., instructions executed, data transferred) a system completes per unit of time, an important metric for evaluating overall system performance.

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Drivers act as a translation layer between generic OS calls and the specific commands a piece of hardware understands, allowing diverse hardware to work with a common operating system interface.

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Synchronous communication uses a common clock to time data transfers precisely, while asynchronous communication uses start/stop signals or handshaking, allowing devices with different or no shared clocks to communicate.

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BIOS (or its modern successor UEFI) is firmware that runs immediately at power-on, performing a Power-On Self-Test (POST), initializing essential hardware, and then handing control to the bootloader to start the OS.

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Parallel processing divides a task into smaller parts that run simultaneously across multiple processing units, potentially reducing total execution time compared to sequential (serial) processing.

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Embedded systems (found in appliances, cars, etc.) are purpose-built for specific tasks, often combining a microcontroller or microprocessor with custom hardware tailored to that function.

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Compiled programs are translated into machine code ahead of time and run directly by the hardware, while interpreted programs are read and executed statement-by-statement by an interpreter at runtime.

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Magnetic storage devices like HDDs and traditional magnetic tape store data by altering the magnetic orientation of particles on a disk or tape surface, read and written by magnetic heads.

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Expansion slots like PCIe provide a standardized interface for adding hardware components (graphics cards, sound cards, network adapters) to extend a computer's functionality beyond its built-in capabilities.

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Pipelining breaks instruction execution into stages (fetch, decode, execute, etc.) so that while one instruction is being decoded, another can be fetched, increasing overall instruction throughput.

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Structural hazards arise from resource conflicts, data hazards from instruction dependencies, and control hazards from branches — all can stall the pipeline and require techniques like forwarding or branch prediction to mitigate.

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Since branches can cause pipeline stalls while waiting to know which path to take, branch predictors guess the likely outcome based on history, allowing speculative execution — if wrong, the pipeline is flushed and corrected.

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Cache hierarchies balance speed and size — L1 is tiny but extremely fast and per-core, L2 is larger but slower, and L3 is the largest and slowest of the on-chip caches, often shared among all cores to reduce main memory access.

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When data needed by the CPU is already in the cache (a "hit"), access is fast; a "miss" requires fetching from slower main memory. A higher hit ratio reduces average memory access time and improves performance.

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Memory-mapped I/O simplifies programming since the same instructions access memory and devices, while port-mapped I/O (used by some architectures like x86 for legacy devices) requires special instructions (e.g., IN/OUT) to access a separate I/O address space.

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Without DMA, the CPU would need to manage every byte of a transfer, wasting cycles; DMA controllers handle bulk transfers independently, significantly improving overall system efficiency for I/O-heavy tasks.

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Endianness determines the byte order of multi-byte data types in memory; this matters when data is shared between systems with different endianness, requiring byte-order conversion (e.g., network byte order is big-endian).

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Paging allows the OS to use disk space as an extension of RAM; when a needed page isn't in physical memory (a page fault), the OS retrieves it from disk (swap/page file), possibly evicting another page to make room.

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Superscalar processors have multiple execution units (e.g., multiple ALUs) and can dispatch several instructions in parallel within a single cycle, increasing instruction-level parallelism beyond what simple pipelining achieves.

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Out-of-order execution allows the CPU to work on instructions whose operands are ready while waiting for others, improving utilization of execution units, while a reorder buffer ensures results are committed in the correct program order.

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SMT allows a core to maintain state for multiple threads and switch between them to fill idle execution slots, improving throughput without the cost of fully duplicating a core, though it doesn't provide the same performance as true additional cores.

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Without coherence protocols (like MESI), one core might read stale data from its cache after another core modifies the shared value; coherence protocols invalidate or update cached copies to maintain consistency across cores.

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By distributing data across multiple memory banks, consecutive accesses can be serviced in parallel or in a pipelined fashion, reducing the effective latency of sequential memory accesses.

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Without a TLB, every memory access would require a potentially slow page-table walk to translate virtual to physical addresses; the TLB caches recent translations, making most accesses much faster.

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Amdahl's Law shows that overall speedup is limited by the portion of a task that cannot be parallelized — even with infinite processors, the non-parallelizable fraction caps the maximum achievable speedup.

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Multiple different microarchitectures (e.g., different generations of Intel chips) can implement the same ISA (e.g., x86-64), each with different internal designs for performance, power, or cost trade-offs.

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An interrupt vector table maps interrupt numbers to handler addresses, so when an interrupt occurs, the CPU can quickly locate and jump to the appropriate interrupt service routine without searching.

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Write-through ensures memory is always up to date but can be slower due to frequent memory writes; write-back is faster for repeated writes to the same line but requires tracking "dirty" cache lines to write back later.

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The MMU enables virtual memory by translating addresses via page tables, and provides isolation between processes by preventing one process from accessing another's memory without permission.

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CPUs exploit ILP via techniques like pipelining, superscalar execution, and out-of-order execution to execute multiple independent instructions concurrently, increasing throughput without changing program semantics.

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TDP gives system designers a target for how much heat the cooling solution (heat sink, fans) must dissipate to keep the CPU within safe operating temperatures under normal conditions.

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In NUMA systems, accessing "local" memory (attached to the same processor) is faster than accessing "remote" memory (attached to another processor), so software performance can depend on memory placement relative to the executing processor.

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Without renaming, reuse of the same register name by independent instructions ("write-after-write" or "write-after-read" hazards) can artificially limit parallelism; renaming maps these to different physical registers, allowing more out-of-order execution.

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Static prediction uses simple compile-time heuristics, while dynamic prediction (using branch history tables, etc.) adapts based on observed program behavior at runtime, generally achieving much higher accuracy.

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For workloads that move large amounts of data (e.g., video processing, scientific computing), memory bandwidth can be a limiting factor even if the CPU itself is fast, since the CPU may stall waiting for data.

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By guessing likely outcomes (e.g., of a branch) and executing ahead of time, the CPU can avoid stalling; if the guess is wrong, the speculative results are discarded, but on average this improves performance — though it has also been linked to security vulnerabilities like Spectre.

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SIMD instructions (like SSE/AVX on x86 or NEON on ARM) allow a single instruction to operate on multiple data values at once, greatly accelerating tasks like multimedia processing and numerical computing that perform the same operation across arrays of data.

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Benchmarks often distinguish between "cold" runs (caches empty, representing first access) and "warm" runs (caches populated from repeated access), since the cache state significantly affects measured performance.

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ECC memory adds extra bits used to detect and correct single-bit (and detect some multi-bit) errors, reducing the risk of data corruption from transient memory errors — commonly used in servers and critical systems.

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Switching between tasks requires saving the current task's register state and loading another's, which takes CPU cycles; frequent context switches can also degrade cache/TLB effectiveness, adding indirect overhead.

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In traditional chipset designs, the northbridge connected the CPU to high-speed components (RAM, GPU), while the southbridge handled lower-speed I/O; many modern CPUs have integrated much of the northbridge functionality directly onto the CPU die.

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By duplicating loop bodies, fewer branch/jump instructions are needed relative to the work done, and the resulting independent operations can be better scheduled and pipelined by the CPU, though at the cost of larger code size.

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Since instructions and data share the same memory and bus in the classic von Neumann architecture, the rate of data transfer between CPU and memory can become a limiting factor — caches and other techniques help mitigate this bottleneck.

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Secure boot uses cryptographic signature verification at each stage of the boot process to ensure that only trusted, signed software runs, helping protect against bootkits and other low-level malware.

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ILP exploits parallelism within a single instruction stream (e.g., via pipelining or superscalar execution), while TLP exploits parallelism across separate threads or processes, often using multiple cores.

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By predicting which memory addresses a program will access next (e.g., sequential array access), prefetchers bring data into cache ahead of time, hiding memory latency and reducing cache misses.

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Vertical scaling ("scaling up") increases the capacity of an individual machine, while horizontal scaling ("scaling out") adds more machines to a system, a distinction relevant to both hardware architecture and distributed systems design.

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Microcode acts as an interpreter layer between the ISA-visible instructions and the underlying hardware control signals, allowing complex instructions to be implemented as sequences of simpler micro-operations, and enabling some bug fixes via microcode updates.

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Since a shared bus can only carry one transaction at a time, arbitration schemes (e.g., priority-based or round-robin) decide which requesting device gets access, preventing collisions and ensuring fair or prioritized access.

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Out-of-order execution can complete instructions in any order, but the architectural state must appear as if instructions executed in program order; the ROB tracks completed instructions and commits results in order, also enabling precise exceptions and speculative execution rollback.

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MESI is a widely used cache coherence protocol where each cache line is tagged with one of four states, governing how reads and writes propagate between caches to maintain a consistent view of memory across cores.

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Spectre and Meltdown exploit the fact that speculatively executed instructions can leave measurable side effects (like cache state changes) even when their results are ultimately discarded, allowing attackers to leak data across security boundaries via timing side channels.

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Since accessing remote memory nodes in a NUMA system incurs higher latency than local memory, NUMA-aware schedulers and allocators try to place a thread's memory on the node local to the CPU executing that thread, reducing cross-node traffic and latency.

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Because cache coherence operates at the granularity of cache lines, two unrelated variables placed on the same line can cause cores to repeatedly invalidate each other's cached copies even though there's no actual data dependency, degrading performance — mitigated by padding/alignment.

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Mechanisms like Tomasulo's algorithm use reservation stations to buffer instructions until their source operands become available, allowing the processor to issue instructions to functional units out of program order while still respecting true data dependencies.

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Huge pages can significantly reduce TLB misses for applications with large memory footprints by covering more memory per TLB entry, but if a process only needs a small portion of a huge page, the unused space is wasted — an internal fragmentation trade-off.

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Even though instructions may execute out of order internally, precise exceptions require the processor to roll back or suppress effects of instructions beyond the faulting one, presenting software (like the OS exception handler) with a clean, in-order-consistent state for correct recovery.

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Many modern CPUs use a "modified Harvard architecture" with separate L1 instruction and data caches, allowing instruction fetches and data accesses to proceed in parallel even though main memory is unified, alleviating the contention implied by the classic von Neumann bottleneck.

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Architectures with relaxed memory models (allowing reordering of loads/stores for performance) require explicit memory barriers/fences at points where ordering matters (e.g., implementing locks), ensuring all cores observe a consistent, expected ordering of operations.

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CPUs may speculatively reorder loads ahead of stores to improve performance, betting that addresses don't overlap; Spectre v4 exploits cases where this speculation is incorrect, allowing an attacker to observe microarchitectural side effects of speculatively loaded (stale or future) values.

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Inclusive caches simplify coherence checks (since checking the larger cache also covers smaller caches' contents) at the cost of some duplicated storage, while exclusive caches maximize effective cache capacity across levels but require more complex coherence handling.

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Hardware or software transactional memory groups operations into atomic transactions; if a conflict with another transaction is detected, the transaction is aborted and retried, providing an alternative to fine-grained locking for concurrent data structure access.

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The choice between virtually and physically indexed/tagged caches involves a trade-off between access latency (avoiding address translation on the critical path) and complications like aliasing, where multiple virtual addresses map to the same physical location, requiring careful handling.

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GPUs achieve massive parallelism by executing groups of threads (warps/wavefronts) in SIMD fashion; when threads within a warp diverge at a branch, the hardware executes both paths sequentially with lane masking, which can reduce efficiency for divergent code.

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Unlike caches, which transparently and automatically cache data based on access patterns, scratchpad memories require explicit software management of what data resides where, offering predictable timing at the cost of increased programming complexity — common in GPUs (shared memory) and DSPs.

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In long-running or fault-prone systems (e.g., HPC clusters), checkpointing periodically saves enough state to recover from failures without losing all prior progress, trading off the overhead of taking checkpoints against the cost of recomputation after a failure.

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Dark silicon reflects the gap between the number of transistors that can be fabricated on a chip and the number that can be simultaneously powered without exceeding thermal design limits, driving architectural trends like specialized accelerators and heterogeneous cores that activate only when needed.

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ROP exploits existing executable code fragments ("gadgets") ending in return instructions, chaining them via a manipulated stack to bypass protections against code injection; hardware features like Intel CET (shadow stacks) or ARM Pointer Authentication help detect or prevent such control-flow hijacking.

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Different architectures (e.g., x86 is relatively strongly ordered, ARM/POWER are weakly ordered) provide different default guarantees about the visibility and ordering of memory operations across cores; weakly ordered architectures require programmers to use memory barriers to achieve the same guarantees that come "for free" on stronger models.