Computer Architecture & Organization MCQ
Test your Computer Architecture & Organization knowledge with 100 multiple choice questions covering fundamentals to advanced concepts, with instant feedback and explanations.
What is the primary role of the CPU (Central Processing Unit) in a computer system?
2What does "ALU" stand for, and what is its function?
3What is the difference between RAM and ROM?
4What is a "register" in CPU architecture?
5What is the "fetch-decode-execute" cycle?
6What is "cache memory" used for?
7What is the difference between "primary storage" and "secondary storage"?
8What does "bus" refer to in computer architecture?
9What is "clock speed" (measured in Hz, e.g., GHz) of a CPU?
10What is the purpose of an "instruction set architecture" (ISA)?
11What is the difference between "CISC" and "RISC" architectures?
12What is a "bit" and a "byte"?
13What is "binary number system" and why is it used in computers?
14What is the function of the "control unit" within a CPU?
15What is a "motherboard"?
16What is "input/output (I/O)" in a computer system?
17What is the purpose of the "program counter" (PC) register?
18What does "word size" refer to in a computer architecture (e.g., 32-bit or 64-bit)?
19What is "firmware" in the context of a computer's hardware?
20What is the purpose of "ports" on a computer (e.g., USB, HDMI)?
21What is the difference between a "32-bit" and "64-bit" operating system in terms of memory addressing?
22What is a "peripheral device"?
23What is the purpose of "virtual memory"?
24What is "overclocking" a CPU?
25What does "multi-core" processor mean?
26What is the purpose of a "heat sink" on a CPU?
27What is "SSD" (Solid State Drive) and how does it differ from a traditional "HDD" (Hard Disk Drive)?
28What is the function of a "GPU" (Graphics Processing Unit)?
29What is "machine code"?
30What is the purpose of an "assembler"?
31What is the purpose of an "address bus" versus a "data bus"?
32What is "throughput" in the context of computer performance?
33What is the role of "device drivers" in a computer system?
34What is the difference between "synchronous" and "asynchronous" data transfer between components?
35What is the purpose of "BIOS/UEFI" during the computer's startup process?
36What is "parallel processing"?
37What does "embedded system" mean in relation to computer architecture?
38What is the difference between a "compiler" and an "interpreter"?
39What is "magnetic storage" and give an example of a device that uses it?
40What is the purpose of an "expansion slot" (e.g., PCIe slot) on a motherboard?
What is "pipelining" in CPU design?
2What is a "pipeline hazard," and what are the main types?
3What is "branch prediction" used for in modern CPUs?
4What is the difference between "L1", "L2", and "L3" cache?
5What is "cache hit ratio" and why does it matter for performance?
6What is "memory-mapped I/O" versus "port-mapped I/O"?
7What is "DMA" (Direct Memory Access) and why is it beneficial?
8What is the difference between "big-endian" and "little-endian" byte ordering?
9What is "virtual memory paging," and what is a "page fault"?
10What is "superscalar" CPU architecture?
11What is "out-of-order execution" in modern CPUs?
12What is "hyper-threading" (or simultaneous multithreading, SMT)?
13What is "cache coherence" in a multi-core/multiprocessor system?
14What is "memory interleaving," and how does it improve performance?
15What is the purpose of a "Translation Lookaside Buffer" (TLB)?
16What is "Amdahl's Law" used to estimate?
17What is "microarchitecture" versus "instruction set architecture" (ISA)?
18What is the purpose of "interrupt vectoring" in handling hardware interrupts?
19What is "write-back" versus "write-through" cache policy?
20What is the role of the "memory management unit" (MMU)?
21What is "instruction-level parallelism" (ILP)?
22What is "thermal design power" (TDP) of a CPU?
23What is "NUMA" (Non-Uniform Memory Access) architecture?
24What is the purpose of "register renaming" in out-of-order processors?
25What is the difference between "static" and "dynamic" branch prediction?
26What is "memory bandwidth," and why does it matter for system performance?
27What is the purpose of "speculative execution" in modern processors?
28What is the difference between "scalar" and "vector" (SIMD) processing?
29What is "cold start" versus "warm cache" in performance benchmarking?
30What is the purpose of "ECC" (Error-Correcting Code) memory?
31What is "context switching" and what overhead does it introduce?
32What is the function of a "northbridge" and "southbridge" in older motherboard chipset designs?
33What is "loop unrolling" as a compiler optimization technique, and how does it relate to CPU architecture?
34What is the significance of the "von Neumann bottleneck"?
35What is "firmware-based secure boot" intended to protect against?
36What is "thread-level parallelism" (TLP), and how does it differ from instruction-level parallelism (ILP)?
37What is the purpose of "prefetching" in CPU memory systems?
38What is the difference between "vertical scaling" and "horizontal scaling" from a hardware architecture perspective?
39What is "microcode" in CPU design?
40What is the purpose of "bus arbitration" in a system with multiple devices sharing a common bus?
In a deeply pipelined superscalar processor, what is the purpose of a "reorder buffer" (ROB)?
2What is the "MESI" cache coherence protocol, and what do its four states represent?
3What vulnerability class do "Spectre" and "Meltdown" exploit, and what architectural feature do they target?
4In NUMA systems, what is "NUMA-aware" memory allocation, and why does it matter for performance?
5What is "false sharing" in the context of multi-core cache coherence, and why is it a performance problem?
6What is the difference between "in-order" and "out-of-order" issue with respect to a processor's "scoreboard" or "reservation stations"?
7In virtual memory systems, what is the trade-off involved in choosing a larger page size (e.g., "huge pages")?
8What does "precise exception" handling mean in the context of out-of-order processors?
9What architectural feature allows a processor to mitigate the "von Neumann bottleneck" for instruction fetch specifically?
10What is the purpose of "memory barriers" (fences) in multi-core/multi-threaded programming on modern architectures with relaxed memory models?
11What is "speculative store bypass" and how does it relate to security vulnerabilities like Spectre variant 4?
12In a multi-level cache hierarchy, what is the difference between "inclusive" and "exclusive" cache designs?
13What is "transactional memory" in computer architecture, and what problem does it aim to solve?
14What is the architectural significance of "tagged" caches versus "physically indexed, physically tagged" (PIPT) caches with respect to virtual memory?
15What is "wavefront" or "warp" scheduling in GPU architectures, and how does it relate to SIMD execution?
16What is the role of "scratchpad memory" in some specialized embedded and GPU architectures, compared to traditional cache?
17What is "checkpoint and restart" (or "checkpointing") in the context of fault-tolerant computer architecture?
18In the context of "dark silicon," what architectural challenge does this term describe for modern chip design?
19What is "return-oriented programming" (ROP) as a security concern related to computer architecture, and what architectural feature helps mitigate it?
20What is the architectural distinction between a "weakly ordered" and "strongly ordered" memory consistency model, and what implication does this have for software?