What architectural feature allows a processor to mitigate the "von Neumann bottleneck" for instruction fetch specifically?
Correct! Well done.
Incorrect.
The correct answer is A) A separate instruction cache (I-cache) from the data cache (D-cache), implementing a Harvard-like split at the cache level, allows simultaneous instruction fetch and data access despite a unified main memory
Correct Answer
A separate instruction cache (I-cache) from the data cache (D-cache), implementing a Harvard-like split at the cache level, allows simultaneous instruction fetch and data access despite a unified main memory
Many modern CPUs use a "modified Harvard architecture" with separate L1 instruction and data caches, allowing instruction fetches and data accesses to proceed in parallel even though main memory is unified, alleviating the contention implied by the classic von Neumann bottleneck.