Intermediate
Digital Logic Design
Q72 / 100
What is a "race condition" in an asynchronous sequential circuit?
Correct! Well done.
Incorrect.
The correct answer is A) A situation where two or more signals change state nearly simultaneously, and the final stable state of the circuit depends unpredictably on the order or timing of those changes
A
Correct Answer
A situation where two or more signals change state nearly simultaneously, and the final stable state of the circuit depends unpredictably on the order or timing of those changes
Explanation
In asynchronous circuits, if multiple state variables must change at once, differing propagation delays can cause the circuit to settle into different final states depending on which signal changes first — a "critical race" that designers must avoid through careful state assignment.
Progress
72/100