In a multi-core embedded SoC running an RTOS, what additional complexity does "cache coherency" introduce when multiple cores access shared memory?
Correct! Well done.
Incorrect.
The correct answer is A) Each core may have its own cache holding a copy of shared data; without coherency mechanisms, one core could read stale data after another core modifies its cached copy, requiring hardware or software coordination to keep views of memory consistent
Correct Answer
Each core may have its own cache holding a copy of shared data; without coherency mechanisms, one core could read stale data after another core modifies its cached copy, requiring hardware or software coordination to keep views of memory consistent
Without coherency protocols (or explicit cache management like flush/invalidate operations), one core's cached value of shared data could become inconsistent with what another core has written, leading to subtle bugs — a major consideration in multi-core embedded designs.